Display device

ABSTRACT

A display device includes a first transistor. The first transistor includes an oxide semiconductor layer, a first gate electrode facing the oxide semiconductor layer and a gate insulating layer between the oxide semiconductor layer and the first gate electrode. The first gate electrode has hydrogen storage properties.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.

17/716,070 filed on Apr. 8, 2022, which application is based upon andclaims the benefit of priority from the prior Japanese PatentApplication No. 2021-066632 filed on Apr. 9, 2021 and the prior JapanesePatent Application No. 2022-024957 filed on Feb. 21, 2022, the entirecontents of which are incorporated herein by reference.

FIELD

One embodiment of the present invention relates to a display device. Inparticular, one embodiment of the present invention relates to a displaydevice using a transistor having an oxide semiconductor.

BACKGROUND

Recently, a transistor using an oxide semiconductor as a channel hasbeen developed in place of an amorphous silicon, a low-temperaturepolysilicon, and a single-crystal silicon (e.g., Japanese laid-openpatent publication No. 2015-187701 and Japanese laid-open patentpublication No. 2020-025114). The transistor using the oxidesemiconductor as the channel is formed in a simple-structured,low-temperature process similar to a transistor using an amorphoussilicon as a channel. It is known that the transistor using the oxidesemiconductor as the channel has higher mobility than the transistorusing the amorphous silicon as the channel and has a very lowoff-current.

In order for a transistor in which oxide semiconductor is used as achannel to have a stable operation, it is essential to reduce oxygenvacancies formed in the oxide semiconductor by supplying more oxygen tothe oxide semiconductor in a manufacturing process for the transistor.As one method for supplying oxygen to the oxide semiconductor, Japaneselaid-open patent publication No. 2015-187701 and Japanese laid-openpatent publication No. 2020-025114 disclose a technique in which aninsulating layer covering the oxide semiconductor is formed under thecondition such that an insulating layer contains more oxygen.

For example, hydrogen-containing layers are used in a transistor used ina display device. For example, a hydrogen-containing layer may be usedas an insulating layer for insulating stacked conductive layers whichare adjacent to each other. When the hydrogen emitted from theinsulating layer reaches an oxide semiconductor layer constituting thetransistor, the oxide semiconductor is reduced. Consequently, oxygendeficiencies formed in the oxide semiconductor are increased, theelectrical characteristics of the transistor varies (e.g., a thresholdvoltage is negatively shifted), and there are problems in thereliability of the display device in which the transistor is used.

SUMMARY

A display device according to an embodiment of the present disclosureincludes a first transistor. The first transistor includes an oxidesemiconductor layer, a first gate electrode facing the oxidesemiconductor layer and a gate insulating layer between the oxidesemiconductor layer and the first gate electrode. The first gateelectrode has hydrogen storage properties.

A display device according to an embodiment of the present disclosureincludes a first transistor. The first transistor includes an oxidesemiconductor layer, a first gate electrode facing the oxidesemiconductor layer and a gate insulating layer between the oxidesemiconductor layer and the first gate electrode. The first gateelectrode includes a first conducive layer capable of forming a metalhydride on a surface of the first conducive layer.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a cross-sectional view showing an outline of a display deviceaccording to an embodiment of the present invention;

FIG. 1B is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 2 is a plan view showing an outline of a display device accordingto an embodiment of the present invention;

FIG. 3 is a plan view illustrating a layout of each layer in a displaydevice according to an embodiment of the present invention;

FIG. 4 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 5 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 6 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 7 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 8 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 9 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 10 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 11 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 12 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 13 is a plan view illustrating a layout of one or more layers in adisplay device according to an embodiment of the present invention;

FIG. 14 is a cross-sectional view showing an outline of a display deviceaccording to an embodiment of the present invention;

FIG. 15 is a plan view showing an outline of a display device accordingto an embodiment of the present invention;

FIG. 16 is a block diagram showing a circuit configuration of a displaydevice according to an embodiment of the present invention; and

FIG. 17 is a circuit diagram showing a pixel circuit of a display deviceaccording to an embodiment of the present invention;

FIG. 18 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 19 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 20 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 21 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 22 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 23 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 24 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention;

FIG. 25 is a cross-sectional view showing a structure of a transistoraccording to an embodiment of the present invention; and

FIG. 26 is a cross-sectional photograph of a transistor according to anembodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention will be described below withreference to the drawings. The following disclosure is merely anexample. A configuration that can be easily conceived by a personskilled in the art by appropriately changing the configuration of theembodiment while maintaining the gist of the invention is naturallyincluded in the scope of the present invention. For the sake of clarityof description, the drawings may be schematically represented withrespect to widths, thicknesses, shapes, and the like of the respectiveportions in comparison with actual embodiments. However, the shape shownis merely an example and does not limit the interpretation of thepresent invention. In this specification and each of the drawings, thesame symbols are assigned to the same components as those describedpreviously with reference to the preceding drawings, and a detaileddescription thereof may be omitted as appropriate.

In the embodiments of the present invention, a direction from asubstrate to an oxide semiconductor layer is referred to as upper orabove. On the contrary, a direction from the oxide semiconductor layerto the substrate is referred to as lower or below. As described above,for convenience of explanation, although the phrase “above” or “below”is used for explanation, for example, a vertical relationship betweenthe substrate and the oxide semiconductor layer may be arranged in adifferent direction from that shown in the drawing. In the followingdescription, for example, the expression “the oxide semiconductor layeron the substrate” merely describes the vertical relationship between thesubstrate and the oxide semiconductor layer as described above, andother members may be arranged between the substrate and the oxidesemiconductor layer. Above or below means a stacking order in astructure in which multiple layers are stacked, and when it is expressedas a pixel electrode above a transistor, it may be a positionalrelationship where the transistor and the pixel electrode do not overlapeach other in a plan view. On the other hand, when it is expressed as apixel electrode vertically above a transistor, it means a positionalrelationship where the transistor and the pixel electrode overlap eachother in a plan view.

“Display device” refers to a structure configured to display an imageusing electro-optic layers. For example, the term display device mayrefer to a display panel including the electro-optic layer, or it mayrefer to a structure in which other optical members (e.g., polarizingmember, backlight, touch panel, etc.) are attached to a display cell.The “electro-optic layer” can include a liquid crystal layer, anelectroluminescence (EL) layer, an electrochromic (EC) layer, and anelectrophoretic layer, as long as there is no technical contradiction.Therefore, although the embodiments described later will be described byexemplifying the liquid crystal display device including a liquidcrystal layer as the display device, the structure in the presentembodiment can be applied to a display device including the otherelectro-optical layers described above.

The expressions “α includes A, B, or C”, “α includes any of A, B, andC”, and “α includes one selected from a group consisting of A, B, and C”do not exclude the case where α includes multiple combinations of A to Cunless otherwise specified. Furthermore, these expressions do notexclude the case where α includes other elements.

The following embodiments may be combined with each other as long asthere is no technical contradiction.

It is an object of one embodiment of the present disclosure to realize ahighly reliable display device.

1. First Embodiment [1-1. Configuration of Display Device 10]

A configuration of a display device 10 according to an embodiment of thepresent invention will be described with reference to FIG. 1A to FIG. 13. FIG. 1A is a cross-sectional view showing an outline of a displaydevice according to an embodiment of the present invention. FIG. 1B is across-sectional view showing a structure of a transistor according to anembodiment of the present invention. FIG. 2 is a plan view showing anoutline of a display device according to an embodiment of the presentinvention. FIG. 3 to FIG. 13 are plan views illustrating layouts of eachlayer in a display device according to an embodiment of the presentinvention. The cross-sectional view in FIG. 1A is for explaining a layerstructure of the display device 10, which may not exactly match the planview in FIG. 2 .

As shown in FIG. 1A, the display device 10 includes a substrate SUB. Thedisplay device 10 also includes a transistor Tr1, a transistor Tr2, awiring W, a connecting electrode ZTCO, a pixel electrode PTCO, a commonauxiliary electrode CMTL, and a common electrode CTCO on the substrateSUB. TCO is an abbreviation for Transparent Conductive Oxide. Thetransistor Tr1 is a transistor included in a pixel circuit of thedisplay device 10. The transistor Tr2 is a transistor included in aperipheral circuit. As will be described in detail later, the peripheralcircuit is a circuit configured to drive the pixel circuit.

[1-2. Configuration of Transistor Tr1]

The transistor Tr1 includes an oxide semiconductor layer OS (OS1, OS2),a gate insulating layer GI1 (first gate insulating layer), and a gateelectrode GL1 (first gate electrode). The gate electrode GL1 faces theoxide semiconductor layer OS. The gate insulating layer GI1 is providedbetween the oxide semiconductor layer OS and the gate electrode GL1. Inthe present embodiment, although a top gate type transistor in which theoxide semiconductor layer OS is provided closer to the substrate SUBthan the gate electrode GL1 is exemplified, a bottom gate typetransistor in which a positional relationship between the gate electrodeGL1 and the oxide semiconductor layer OS is reversed may be applied.

The oxide semiconductor layer OS includes oxide semiconductor layersOS1, OS2. The oxide semiconductor layer OS1 is an oxide semiconductorlayer in an area overlapping the gate electrode GL1 in a plan view. Theoxide semiconductor layer OS1 functions as a semiconductor layer and isswitched between a conductive state and a non-conductive state accordingto a voltage supplied to the gate electrode GL1. That is, the oxidesemiconductor layer OS1 functions as a channel for the transistor Tr1.The oxide semiconductor layer OS2 functions as a conductive layer. Theoxide semiconductor layers OS1, OS2 are layers formed from the sameoxide semiconductor layer. For example, the oxide semiconductor layerOS2 is a low resistance oxide semiconductor layer formed by dopingimpurities into a layer which has the same physical properties as theoxide semiconductor layer OS1.

An insulating layer IL2 is provided above the gate electrode GL1. Awiring W1 is provided above the insulating layer IL2. The wiring W1 isconnected to the oxide semiconductor layer OS2 via an opening WCONprovided in the insulating layer IL2 and the gate insulating layer GI1.A data signal related to pixel gradation is transmitted to the wiringW1. An insulating layer IL3 is provided above the insulating layer IL2and the wiring W1. The connecting electrode ZTCO is provided above theinsulating layer IL3. The connecting electrode ZTCO is connected to theoxide semiconductor layered OS2 via an opening ZCON provided in theinsulating layers IL3, IL2, and the gate insulating layer GI1. Theconnecting electrode ZTCO is in contact with the oxide semiconductorlayer OS2 at the bottom of the opening ZCON. The connecting electrodeZTCO is a transparent conductive layer.

An area where the connecting electrode ZTCO and the oxide semiconductorlayers OS2 are in contact with each other is referred to as a firstcontact area CON1. As will be described in detail later, the connectingelectrode ZTCO is in contact with the oxide semiconductor layer OS2 inthe first contact area CON1 not overlapping the gate electrode GL1 andthe wiring W1 in a plan view. The first contact area CON1 is included inthe display area of a pixel in a plan view.

For example, when a transparent conductive layer such as an ITO layer isformed in contact with a semiconductor layer such as a silicon layer, asurface of the semiconductor layer is oxidized by a process gas oroxygen ions at the time of a deposition of an ITO film. Since an oxidelayer formed on the surface of the semiconductor layer is highresistance, a contact resistance between the semiconductor layer and thetransparent conductive layer is increased. As a result, there is adefect in an electrical contact between the semiconductor layer and thetransparent conductive layer. On the other hand, even if the abovetransparent conductive layer is formed so as to be in contact with theoxide semiconductor layer, a high resistance oxide layer as describedabove is not formed on a surface of the oxide semiconductor layer.Therefore, there is no defect in the electrical contact between theoxide semiconductor layer and the transparent conductive layer.

An insulating layer IL4 is provided above the connecting electrode ZTCO.The insulating layer IL4 eases (flattens) a step formed from a structureprovided below the insulating layer IL4. The insulating layer IL4 may bereferred to as a planarization film. The pixel electrode PTCO isprovided above the insulating layer IL4. The pixel electrode PTCO isconnected to the connecting electrode ZTCO via an opening PCON providedin the insulating layer IL4. An area where the connecting electrode ZTCOand the pixel electrode PTCO are in contact with each other is referredto as a second contact area CON2. The second contact area CON2 overlapsthe gate electrode GL1 in a plan view. The pixel electrode PTCO is atransparent conductive layer.

An insulating layer IL5 is provided above the pixel electrode PTCO. Thecommon auxiliary electrode CMTL and the common electrode CTCO areprovided above the insulating layer IL5. That is, the pixel electrodePTCO faces the common electrode CTCO via the insulating layer IL5. Thecommon electrode CTCO is connected to the common auxiliary electrodeCMTL at the opening PCON (in the second contact area CON2). As will bedescribed in detail later, the common auxiliary electrode CMTL and thecommon electrode CTCO have different patterns respectively when seen ina plan view. The common auxiliary electrode CMTL is a metal layer. Thecommon electrode CTCO is a transparent conductive layer. The electricresistance of the common auxiliary electrode CMTL is lower than theelectric resistance of the common electrode CTCO. The common auxiliaryelectrode CMTL also functions as a light-shielding layer. For example,the common auxiliary electrode CMTL shields light from adjacent pixelsto suppress color mixing from occurring. A spacer SP is provided abovethe common electrode CTCO.

The spacer SP is provided for a part of the pixels. For example, thespacer SP may be provided for any one of a blue pixel, a red pixel and agreen pixel. However, the spacer SP may be provided for all the pixels.A height of the spacer SP is half the height of a cell gap. A spacer isalso provided on a counter substrate, and the spacer on the countersubstrate and the above spacer SP overlap in a plan view.

A light-shielding layer LS is provided between the transistor Tr1 andthe substrate SUB. In the present embodiment, light-shielding layersLS1, LS2 are provided as the light-shielding layer LS. However, thelight-shielding layer LS may be formed of only the light-shielding layerLS1 or LS2. In a plan view, the light-shielding layer LS is provided inan area where the gate electrode GL1 and the oxide semiconductor layerOS overlap. That is, in a plan view, the light-shielding layer LS isprovided in an area overlapping the oxide semiconductor layer OS1. Thelight-shielding layer LS suppresses the light incident from thesubstrate SUB side from reaching the oxide semiconductor layer OS1. Inthe case where a conductive layer is used as the light-shielding layerLS, a voltage may be applied to the light-shielding layer LS to controlthe oxide semiconductor layer OS1. In the case where a voltage isapplied to the light-shielding layer LS, the light-shielding layer LSand the gate electrode GL1 may be connected by a peripheral area of thepixel circuit. In a plan view, the above first contact area CON1 isprovided in an area not overlapping the light-shielding layer LS.

[1-3. Configuration of Transistor Tr2]

The transistor Tr2 has a p-type transistor Tr2-1 and an n-typetransistor Tr2-2. The transistor Tr2 may be referred to as a “secondtransistor.”

The p-type transistor Tr2-1 and the n-type transistor Tr2-2 both includea gate electrode GL2, a gate insulating layer G12, and a semiconductorlayer S (S1, S2 and S3). The gate electrode GL2 faces the semiconductorlayer S. The gate insulating layer G12 is provided between thesemiconductor layer S and the gate electrode GL2. In the presentembodiment, although a bottom gate type transistor in which the gateelectrode GL2 is provided closer to the substrate SUB than thesemiconductor layer S is exemplified, a top gate type transistor inwhich a positional relationship between the semiconductor layer S andthe gate electrode GL2 is reversed may be used as the display device.The gate electrode GL2 may be referred to as a “second gate electrode”.The gate insulating layer G12 may be referred to as a “second gateinsulating layer”.

The semiconductor layer S of the p-type transistor Tr2-1 includessemiconductor layers S1 and S2. The semiconductor layer S of the n-typetransistor Tr2-2 includes the semiconductor layers S1, S2 and S3. Thesemiconductor layer S1 is a semiconductor layer overlapping the gateelectrode GL2 in a plan view. The semiconductor layer S1 functions as achannel for the transistors Tr2-1 and Tr2-2. The semiconductor layer S2functions as a conductive layer. The semiconductor layer S3 functions asa conductive layer with a higher resistance than the semiconductor layerS2. The semiconductor layer S3 suppresses hot carrier degradation byattenuating hot carriers intruding toward the semiconductor layer S1.

An insulating layer IL1 and the gate insulating layer GI1 are providedon the semiconductor layer S. In the transistor Tr2, the gate insulatinglayer GI1 simply functions as an interlayer film (first insulatinglayer). That is, the first insulating layer covers the transistor Tr2.In this case, the first insulating layer is arranged in the same layeras the gate insulating layer GI1. A wiring W2 is provided above theseinsulating layers. The wiring W2 is connected to the semiconductor layerS via an opening provided in the insulating layer IL1 and the gateinsulating layer GI1. The insulating layer IL2 is provided on the wiringW2. The wiring W1 is provided on the insulating layer IL2. The wiring W1is connected to the wiring W2 via an opening provided in the insulatinglayer IL2.

As shown in FIG. 1A, the gate electrode GL2 provided in the peripheralcircuit and a light shielding layer LS2 provided in the pixel circuitare arranged in the same layer. The wiring W2 provided in the peripheralcircuit (first peripheral circuit wiring) and the gate electrode GL1provided in the pixel circuit (first gate electrode) are arranged in thesame layer. In the peripheral circuit, the wiring W2 is connected to thewiring W3 (second peripheral circuit) provided in the same layer as thegate electrode GL2 via a contact hole, which is formed in insulatinglayers (the gate insulating layer GI1, the insulating layer IL1, thegate insulating layer GI2) and penetrates the insulating layers. Thesame layer means that a plurality of members are formed from onepatterned layer or are simultaneously formed by patterning the samesingle layer material or the same laminated materials in the sameprocess. That is, a thickness of each layer of the gate electrode GL1and a taper angle of each layer of the gate electrode GL1 aresubstantially the same as a thickness of each layer of the wiring W2 anda taper angle of each layer of the wiring W2.

[1-4. Configuration of Gate Electrode GL1]

A detailed cross-sectional configuration of the gate electrode GL1 willbe described with reference to FIG. 1B. As shown in FIG. 1B, the gateelectrode GL1 has a first conductive layer 110, a second conductivelayer 120, and a third conductive layer 130. The first conductive layer110 is provided above the gate insulating layer GI1 and is in contactwith the gate insulating layer GI1. The second conductive layer 120 isprovided above the first conductive layer 110 and is in contact with thefirst conductive layer 110. The third conductive layer 130 is providedabove the second conductive layer 120 and is in contact with the secondconductive layer 120.

A side part of each of the first conductive layer 110, the secondconductive layer 120, and the third conductive layer 130 has a taperedshape with an inclined surface facing upward. In FIG. 1B, an angleformed by the inclined surface and the gate insulating layer GI1 (or anupper surface of the substrate SUB or the horizontal surface) isreferred to as a taper angle θ. In FIG. 1B, although the tapered shapesin which sides of these conductive layers are arranged on a straightline is shown, the present invention is not limited to thisconfiguration. For example, tilted angles of the side surfaces of theconductive layers may be different from each other. An upper end of theside surface of the first conductive layer 110 may not coincide with alower end of the side surface of the second conductive layer 120.Similarly, an upper end of the side surface of the second conductivelayer 120 may not coincide with a lower end of the side surface of thethird 130. For example, a part of the upper surface of the firstconductive layer 110 may be exposed from the second conductive layer120. Similarly, a part of the upper surface of the second conductivelayer 120 may be exposed from the third conductive layer 130.

A material having hydrogen storage properties is used as the firstconductive layer 110 and the third conductive layer 130. In other words,a material capable of forming a metal hydride on a surface thereof isused as the first conductive layer 110 and the third conductive layer130. Specifically, titanium (Ti), magnesium (Mg), vanadium (V), rantan(La), and alloys containing these materials are used as the firstconductive layer 110 and the third conductive layer 130. For example,when Ti is used as the first conductive layer 110 and the thirdconductive layer 130, the Ti absorbs water and hydrogen contained in theacidic liquid in the manufacturing process to form a metal hydride(TiH₂). In this manner, the first conductive layer 110 and the thirdconductive layer 130 have hydrogen storage properties by forminghydrides from the above materials such as Ti.

A material having lower resistance than the first conductive layer 110and the third conductive layer 130 is used as the second conductivelayer 120. For example, aluminum (Al), molybdenum (Mo), tungsten (W),silver (Ag), and an alloy containing these materials (for example, analloy of molybdenum and tungsten) are used as the second conductivelayer 120.

[1-5. Plane Layout of Display Device 10]

A plane layout of a pixel of the display device 10 will be describedwith reference to FIG. 2 to FIG. 13 . In FIG. 2 , the pixel electrodePTCO, the common auxiliary electrode CMTL, the common electrode CTCO,and the spacer SP are omitted. The plane layout of the pixel electrodePTCO, the common auxiliary electrode CMTL, and the common electrode CTCOare shown in FIG. 11 to FIG. 13, respectively.

As shown in FIG. 2 and FIG. 3 , the light-shielding layer LS extends ina direction D1. A shape of the light-shielding layer LS may be differentdepending on the pixel. In the present embodiment, a protruding part PJTprotruding in a direction D2 is provided from a part of thelight-shielding layer LS extending in the direction D1. As shown in FIG.5 , the light-shielding layer LS is provided in an area including thearea where the gate electrode GL1 and the oxide semiconductor layer OSoverlap in a plan view. The gate electrode GL1 can also be referred toas a “gate line.”

As shown in FIG. 2 , FIG. 4 , and FIG. 5 , the oxide semiconductor layerOS extends in the direction D2. The gate electrode GL1 extends in thedirection D1 so as to intersect the oxide semiconductor layer OS. Apattern of the gate electrode GL1 is provided inside a pattern of thelight-shielding layer LS. In other words, the oxide semiconductor layersOS is formed in a long shape intersecting the gate electrode GL1.

As shown in FIG. 2 , FIG. 6 , and FIG. 7 , the opening WCON is providedin an area overlapping the wiring W1 near an upper end of the pattern ofthe oxide semiconductor layer OS. A main part of the pattern of theoxide semiconductor layer OS extends in the direction D2 between a pairof the adjacent wirings W1. The remaining part of the pattern of theoxide semiconductor layer OS extends obliquely in the direction D1 andthe direction D2 from the main part and overlaps the opening WCON.

As shown in FIG. 2 and FIG. 7 , multiple wirings W1 extend in thedirection D2. In the case where the adjacent wirings W1 need to bedescribed separately, the adjacent wiring W1 is referred to as a wiringW1-1 (first pixel wiring) and a wiring W1-2 (second pixel wiring). Inthis case, it can be said that the main part of the oxide semiconductorlayer OS extends in the direction D2 between the first pixel wiring W1-1and the second pixel wiring W1-2, and intersects the gate electrode GL1.In other words, the oxide semiconductor layer OS is provided in a longshape in the direction D2 (shape having a longitudinal) and connected tothe wiring W1-1 at one end in a longitudinal direction of the oxidesemiconductor layer OS.

As shown in FIG. 2 , FIG. 8 , and FIG. 9 , the opening ZCON is providednear a lower end of the pattern of the oxide semiconductor layer OS. Theopening ZCON is provided in an area overlapping the pattern of the oxidesemiconductor layer OS and not overlapping the gate electrode GL1. Theopening ZCON is provided in an area overlapping the connecting electrodeZTCO. The connecting electrode ZTCO overlaps the gate electrode GL1 andthe oxide semiconductor layer OS between the wiring W1-1 and the wiringW1-2. Therefore, the connecting electrode ZTCO is in contact with theoxide semiconductor layer OS in the opening ZCON (the first contact areaCON1) not overlapping the gate electrode GL1.

In other words, the oxide semiconductor layer OS is connected to theconnecting electrode ZTCO (the first transparent conductive layer) atthe other end in the longitudinal direction of the oxide semiconductorlayer OS. The connecting electrode ZTCO is formed in a long shapeextending in the direction D2 similar to the oxide semiconductor layerOS. In the direction D1, a width of the connecting electrode ZTCO issmaller than a width of the oxide semiconductor layer OS.

As shown in FIG. 2 , FIG. 7 , and FIG. 8 , the oxide semiconductor layerOS is in contact with the wiring W1 at the opposite side of the openingZCON with respect to the gate electrode GL1. The opening ZCON does notoverlap the light-shielding layer LS.

As shown in FIG. 2 , FIG. 10 , and FIG. 11 , the opening PCON isprovided near an upper end of a pattern of the connecting electrodeZTCO. The opening PCON is provided in an area overlapping the pattern ofthe gate electrode GL1 and the pattern of the connecting electrode ZTCO.The opening PCON is provided in an area overlapping the pixel electrodePTCO. The pixel electrode PTCO overlaps the gate electrode GL1, theoxide semiconductor layer OS, and the connecting electrode ZTCO betweenthe wiring W1-1 and the wiring W1-2. Therefore, the pixel electrode PTCOis in contact with the connecting electrode ZTCO in the opening PCON(the second contact area CON2) overlapping the gate electrode GL1.

The pixel electrode PTCO extends in the translucent area as describedbelow. The pixel electrode PTCO may be referred to as a “secondtransparent conductive layer”. In other words, the pixel electrode PTCO(the second transparent conductive layer) is formed in an elongatedshape extending in the direction D2 similar to the oxide semiconductorlayer OS and the wiring W1-1 (the first pixel wiring). In the directionD1, a width of the pixel electrode PTCO (the second transparentconductive layer) in a portion where the opening PCON is provided islarger than a width of the oxide semiconductor layer OS.

As shown in FIG. 11 , the connecting electrode ZTCO (the firsttransparent conductive layer) is formed in an elongated shape extendingalong the wiring W1-1 (the first pixel wiring). In the direction D1, awidth of the opening PCON constituting the second contact area CON2 islarger than a width of the connecting electrode ZTCO (the firsttransparent conductive layer). In a plan view, the entire connectingelectrode ZTCO (the first transparent conductive layer) overlaps thepixel electrode PTCO (the second transparent conductive layer).

As shown in FIG. 11 , the pixel electrodes PTCO are aligned in thedirection D2. Among the pixels adjacent in the direction D2, one of thepixels is referred to as a “first pixel”, and another of the pixels isreferred to as a “second pixel”. For example, the first pixel is a pixelcorresponding to the upper pixel electrode PTCO among the pixelelectrodes PTCO arranged in the direction D2 in FIG. 11 , and the secondpixel is a pixel corresponding to the lower pixel electrode PTCO amongthe pixel electrodes PTCO arranged in the direction D2. In this case,pixel signals are supplied from the wiring W1-1 (the first pixel wiring)to the first pixel and the second pixel.

The pixel electrodes PTCO are aligned in the direction D1. A pixeladjacent in the direction D1 with respect to the first pixel describedabove is referred to as a “third pixel”, and a pixel adjacent in thedirection D1 with respect to the second pixel described above isreferred to as a “fourth pixel”. The third pixel and the fourth pixelare adjacent to each other in the direction D2. Pixel signals aresupplied from the wiring W1-2 (the second pixel wiring) adjacent to thewiring W1-1 (the first pixel wiring) to the third pixel and the fourthpixel.

As described above, each of the first pixel, the second pixel, the thirdpixel, and the fourth pixel has the transistor Tr1 (a pixel transistor),the connecting electrode ZTCO (the first transparent conductive layer),and the pixel electrode PTCO (the second transparent conductive layer).

The transistor Tr1 includes the oxide semiconductor layer OS, the gateelectrode GL1 facing the oxide semiconductor layer OS, and the gateinsulating layer GI1 between the oxide semiconductor layer OS and thegate electrode GL1. The connecting electrode ZTCO overlaps the gateelectrode GL1 and the oxide semiconductor layer OS in a plan view, andis in contact with the oxide semiconductor layer OS in the opening ZCON(the first contact area CON1) which does not overlap the gate electrodeGL1. The pixel electrode PTCO overlaps the gate electrode GL1, the oxidesemiconductor layer OS, and the connecting electrode ZTCO in a planview, and is connected to the connecting electrode ZTCO in the openingPCON (the second contact area CON2) which overlaps the gate electrodeGL1.

In a plan view, the pixel electrode PTCO of the first pixel provided inan upper side of FIG. 11 overlaps the oxide semiconductor layer OS ofthe first pixel and the oxide semiconductor layer OS of the second pixelprovided in a lower side of the first pixel. The pixel electrode PTCO ofthe first pixel overlaps the oxide semiconductor layer OS of the fourthpixel in a plan view.

As shown in FIG. 12 , the common auxiliary electrode CMTL is provided ina grid shape so as to surround the periphery of a pixel area. That is,the common auxiliary electrode CMTL is provided commonly for multiplepixels. In other words, the common auxiliary electrode CMTL has anopening OP. The opening OP is provided to expose the pixel electrodePTCO. A pattern of the opening OP is provided inside the pattern of thepixel electrode PTCO. An area provided with the opening OP correspondsto a display area. That is, the opening ZCON is included in the displayarea. The display area means an area in which a user can see light froma pixel. For example, a frame area that is shielded by a metal layer andunperceivable to the user is not included in the display area. That is,the above display area may be referred to as a “translucent area (oropening area)”.

As shown in FIG. 13 , the common electrode CTCO is provided commonly formultiple pixels. A slit SL is provided in an area corresponding to theabove opening OP. The slit SL has a curved shape (longitudinally longS-shape). A tip of the slit SL has a shape in which a width orthogonalto an extending direction of the tip is reduced. Referring to FIG. 1Aand FIG. 13 , the common electrode CTCO has the slit SL at a positionfacing the pixel electrode PTCO.

[1-6. Materials of Each Member of Display Device 10]

A rigid substrate having light transmittance and no flexibility, such asa glass substrate, a silica substrate, and a sapphire substrate can beused as the substrate SUB. On the other hand, in the case where thesubstrate SUB needs to have flexibility, a flexible substrate containinga resin and having flexibility, such as a polyimide substrate, anacrylic substrate, a siloxane substrate, or a fluororesin substrate canbe used as the substrate SUB. In order to improve the heat resistance ofthe substrate SUB, impurities may be introduced into the above resin.

General metal materials can be used as the gate electrode GL2, thewirings W1, W2, the light-shielding layer LS, and the common auxiliaryelectrode CMTL. For example, aluminum (Al), titanium (Ti), chromium(Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum(Ta), tungsten (W), bismuth (Bi), and silver (Ag), or alloys orcompounds thereof are used as members of these electrodes and the like.The above materials may be used in a single layer or a stacked layer asthe members of the above electrodes and the like.

General insulating materials can be used as the gate insulating layersGI1, G12, and the insulating layers IL1 to IL5. For example, inorganicinsulating layers such as silicon oxide (SiO_(x)), silicon oxynitride(SiO_(x)N_(y)), silicon nitride (SiN_(x)), silicon nitride oxide(SiN_(x)O_(y)), aluminum oxide (AlO_(x)), aluminum oxynitride(AlO_(x)N_(y)), aluminum nitride oxide (AlN_(x)O_(y)), aluminum nitride(AlN_(x)), and the like can be used as the insulating layers IL1 to IL3,and IL5. Low-defect insulating layers can be used as these insulatinglayers. Organic insulating materials such as a polyimide resin, anacrylic resin, an epoxy resin, a silicone resin, a fluororesin, or asiloxane resin can be used as the insulating layer IL4. The aboveorganic insulating materials may be used as the gate insulating layersGI1, G12, and the insulating layers IL1 to IL3, IL5. The above materialsmay be used in a single layer or a stacked layer as a member of theinsulating layer and the like.

SiO_(x) with a thickness of 100 nm is used as the gate insulating layerGI1 as an example of the above insulating layer. SiO_(x)/SiN_(x)/SiO_(x)with a total thickness of 600 nm to 700 nm is used as the insulatinglayer IL1. SiO_(x)/SiN_(x) with a total thickness of 60 nm to 100 nm isused as the gate insulating layer GI2. SiO_(x)/SiN_(x)/SiO_(x) with atotal thickness of 300 nm to 500 nm is used as the insulating layer IL2.SiO_(x) with a total thickness of 200 nm to 500 nm (single layer),SiN_(x) (single layer), or a stacked layer thereof is used as theinsulating layer IL3. The organic layer with a thickness of 2 μm to 4 μmis used as the insulating layer IL4. SiN_(x) (single layer) with athickness of 50 nm to 150 nm is used as the insulating layer IL5.

The above SiO_(x)N_(y) and AlO_(x)N_(y) are silicone compounds andaluminum compounds containing nitrogen (N) in a smaller ratio (x>y) thanoxygen (O).

The above SiN_(x)O_(y) and AlN_(x)O_(y) are silicon compounds andaluminum compounds containing oxygen in a smaller ratio (x>y) thannitrogen.

A metal oxide having semiconductor characteristics can be used as theoxide semiconductor layer OS. The oxide semiconductor layer OS has lighttransmittance. For example, an oxide semiconductor containing indium(In), gallium (Ga), zinc (Zn), and oxygen (O) can be used as the oxidesemiconductor layer OS. In particular, an oxide semiconductor having acomposition ratio of In:Ga:Zn:O=1:1:1:4 can be used. However, the oxidesemiconductor containing In, Ga, Zn, and O used in the presentembodiment is not limited to the above composition, and an oxidesemiconductor having a composition different from that described abovecan also be used. For example, the ratio of In may be larger than thatdescribed above to improve mobility. The ratio of Ga may be larger toincrease the band gap and reduce the influence of light irradiation.

Other elements may be added to the oxide semiconductor containing In,Ga, Zn, and O. For example, a metal element such as Al or Sn may beadded to the oxide semiconductor. In addition to the oxide semiconductordescribed above, an oxide semiconductor containing In and Ga (IGO), anoxide semiconductor containing In and Zn (IZO), an oxide semiconductorcontaining In, Sn, and Zn (ITZO), and an oxide semiconductor containingIn and W may be used as the oxide semiconductor layer OS. The oxidesemiconductor layer OS may be amorphous or crystalline. The oxidesemiconductor layer OS may be a mixed phase of amorphous andcrystalline.

A transparent conductive layer is used as the connecting electrode ZTCO,the pixel electrode PTCO, and the common electrode CTCO. A mixture ofindium oxide and tin oxide (ITO) and a mixture of indium oxide and zincoxide (IZO) can be used as the transparent conductive layer. Materialsother than the above may be used as the transparent conductive layer.

As described above, in a display device 10 according to the presentembodiment, the first conductive layer 110 which has hydrogen storageproperties is used as the gate electrode GL1. Therefore, for example,hydrogen released from the gate insulating layer GI1, the insulatinglayers IL1, IL2, or the like is stored in the first conductive layer110. Consequently, since hydrogen that may reduce the oxidesemiconductor layer OS can be reduced particularly around the oxidesemiconductor layer, fluctuations in the electrical characteristic ofthe transistor Tr1 are suppressed.

In particular, in the case where the transistor Tr1 in which an oxidesemiconductor layer is used for a channel and a transistor Tr2 in whicha semiconductor layer made of polysilicon is used for a channel areformed on the same substrate, a silicon nitride layer containing a largeamount of hydrogen in its film is used to improve the characteristic ofthe transistor Tr2. When the hydrogen emitted from the silicon nitridelayer reaches the oxide semiconductor layer of the transistor Tr1, theelectrical characteristic of the transistor Tr1 is changed. However,according to the configuration according to the present embodiment, evenin such a case, since the first conductive layer 110 absorbs hydrogen,it is possible to suppress fluctuations in the electrical characteristicof the transistor Tr1 as described above.

Since each conductive layer included in the gate electrode GL1 has atapered shape, the deterioration of the coverage of the insulating layerIL2 in an area where the insulating layer IL2 gets over the gateelectrode GL1 is suppressed. Consequently, it is possible to suppressproblems such as disconnection of the conductive layers formed on theinsulating layer IL2. Therefore, a highly reliable display device can berealized.

[1-7. Modifications of Display Device 10]

A modification of the display device 10 will be described with referenceto FIG. 18 to FIG. 21 . FIG. 18 to FIG. 21 are circuit diagrams showinga pixel circuit of a display device according to an embodiment of thepresent invention. Although the gate electrode GL1 of this modificationis similar to the gate electrode GL1 in FIG. 1B, the layer structure ofboth is different.

[1-7-1. Modification 1]

As shown in FIG. 18 , in Modification 1, a thickness of the thirdconductive layer 130 provided at a position farther from the oxidesemiconductor layer OS than the first conductive layer 110 is smallerthan a thickness of the first conductive layer 110. The thickness of thethird conductive layer 130 is ½ or less or ⅓ or less of the thickness ofthe first conductive layer 110. With the above-described configuration,when the gate electrode GL1 is dry-etched, the taper angle θ₂ of thesecond conductive layer 120 (e.g., Al) can be reduced as compared withthe case where the thickness of the third conductive layer 130 is thesame as the thickness of the first conductive layer 110 (1B in FIG. 3 ).That is, the taper angle θ₂ of the second conductive layer 120 shown inFIG. 18 can be smaller than the taper angle θ of the second conductivelayer 120 shown in FIG. 1B. As a result, the coverage of the insulatinglayer IL2 formed on the gate electrode GL1 can be improved. Although aconfiguration in which the taper angle θ₂ of the second conductive layer120 is smaller (θ₂<θ₁) than the taper angle θ₁ of the first conductivelayer 110 has been shown in FIG. 18 , it is not limited to thisconfiguration. The taper angle θ₁ of the first conductive layer 110 maybe the same as the taper angle θ₂ of the second conductive layer 120(8θ₂=θ₁) and the taper angle θ₁ of the first conductive layer 110 may besmaller than the taper angle θ₂ of the second conductive layer 120(θ₁<θ₂).

[1-7-2. Modification 2]

As shown in FIG. 19 , in Modification 2, a fourth conductive layer 140is provided in place of the third conductive layer 130. The fourthconductive layer 140 is in contact with an upper surface and sidesurfaces of the second conductive layer 120. Further, the fourthconductive layer 140 is in contact with the side surfaces of the firstconductive layer 110 and the gate insulating layer GI1. Similar to thefirst conductive layer 110 and the third conductive layer 130, amaterial having hydrogen storage properties is used as the fourthconductive layer 140. To form this structure, after forming the patternsof the first conductive layer 110 and second conductive layer 120, thefourth conductive layer 140 is deposited, and then a pattern of thefourth conductive layer 140 is formed. That is, since the secondconductive layer 120 is positioned at the uppermost layer when thesecond conductive layer 120 is processed, the taper angle θ₂ of thesecond conductive layer 120 can be smaller than the taper angle θ₁ ofthe first conductive layer 110. Consequently, the coverage of theinsulating layer IL2 formed on the gate electrode GL1 can be improved.As in Modification 1, the taper angle θ₁ of the first conductive layer110 may be the same as the taper angle θ₂ of the second conductive layer120, and the taper angle θ₁ of the first conductive layer 110 may besmaller than the taper angle θ₂ of the second conductive layer 120.

In the case where Al is used as the second conductive layer 120, aprocess of removing a natural oxide film formed on the surface of thesecond conductive layer 120 may be provided before forming the fourthconductive layer 140. For example, in the case where the fourthconductive layer 140 is formed by a sputtering method, the natural oxidefilm may be removed by performing a reverse sputtering treatment on thesurface of the second conductive layer 120 before forming the fourthconductive layer 140.

[1-7-3. Modification 3]

As shown in FIG. 20 , Modification 3 shows a configuration in which thefourth conductive layer 140 is formed on the Modification 1 (FIG. 18 ).That is, in Modification 3, the fourth conductive layer 140 is incontact with the upper surface and the side surfaces of the thirdconductive layer 130. Further, the fourth conductive layer 140 is incontact with the side surfaces of each of the first conductive layer 110and the second conductive layer 120 and the gate insulating layer GI1.To form this structure, after forming the patterns of the firstconductive layer 110 to the third conductive layer 130, the fourthconductive layer 140 is deposited to form the pattern. Also inModification 3, the coverage of the insulating layer IL2 formed on thegate electrode GL1 can be improved as in Modification 1. In such aconfiguration, it is needless to say that a channel length of the oxidesemiconductor layer OS is defined by a distance L between the outer endsof the fourth conductive layer 140. That is, two types of electricallyconnected conductive layers, the first conductive layer 110 and thefourth conductive layer 140, face the oxide semiconductor OS from thesame direction via the gate insulating layer GI1, and these constituteone gate electrode.

[1-7-4. Modification 4]

As shown in FIG. 21 , in Modification 4, a part of the upper surface ofthe first conductive layer 110 is exposed from the second conductivelayer 120. That is, an upper end of the side surface of the firstconductive layer 110 does not coincide with a lower end of the sidesurface of the second conductive layer 120, and in a plan view, thelower end of the side surface of the second conductive layer 120 islocated inside the upper end of the side surface of the first conductivelayer 110. The taper angle 62 of the second conductive layer 120 isequal to the taper angle θ₁of the first conductive layer 110. Asdescribed above, since a part of the upper surface of the firstconductive layer 110 having hydrogen storage properties is exposed fromthe second conductive layer 120, the area of the surface of the firstconductive layer 110 that can store hydrogen can be increased. In theexample of FIG. 21 , although the configuration in which the upper endof the side surface of the second conductive layer 120 coincides withthe lower end of the side surface of the third conductive layer 130 hasbeen exemplified, the present invention is not limited to thisconfiguration. The taper angle θ₂ of the second conductive layer 120 maybe different from the taper angle θ₁ of the first conductive layer 110.

[1-7-5. Modification 5]

As shown in FIG. 22 , although Modification 5 is similar to thestructure of Modification 2 (FIG. 19 ), it is different fromModification 2 in the structure of the fourth conductive layer 140.Specifically, in Modification 5, the fourth conductive layer 140 extendsoutward from the end of the first conductive layer 110. In other words,in the area that does not overlap the first conductive layer 110 in aplan view, both the lower and upper surfaces of the fourth conductivelayer 140 in a cross-sectional view are parallel to the upper surface ofthe gate insulating layer GI1. In this configuration, the channel lengthof the oxide semiconductor layer OS is defined by the distance L betweenthe outer ends of the fourth conductive layer 140.

[1-7-6. Modification 6]

As shown in FIG. 23 , although Modification 6 is similar to thestructure of Modification 4 (FIG. 21 ), it is different fromModification 4 in the structure of the second conductive layer 120.Specifically, in a pattern end of the second conductive layer 120, it isdifferent from Modification 4 in that the angle θ₂ formed by the lowersurface and the side surface of the second conductive layer 120 is asubstantially right angle, and that the area of a part of the uppersurface of the first conductive layer 110 is not covered by the secondconductive layer 120 and the upper surface of the first conductive layer110 is in contact with the insulating layer IL2 in area.

In Modification 6, the taper angle θ₂ of the second conductive layer 120is larger than the taper angle θ₁ of the first conductive layer 110 anda taper angle θ₃ of the third conductive layer 130. The taper angle θ₁of the first conductive layer 110 may be the same as or different fromthe taper angle θ₃ of the third conductive layer 130. The taper angle θ₂of the second conductive layer 120 need not be strictly at a right angle(90°), but may be substantially at a right angle. For example, the taperangle of the second conductive layer 120 may be 85° or more and 95° orless.

[1-7-7. Modification 7]

As shown in FIG. 24 , although Modification 7 is similar to thestructure of Modification 6 (FIG. 23 ), it is different fromModification 6 in the taper angle θ₁ to taper angle θ₃. In Modification7, the taper angle θ₂ is a sharp angle. Further, the taper angle θ₁ andthe taper angle θ₃ are smaller angles than the taper angle θ₂. The taperangle θ₁ and the taper angle θ₃ are substantially the same. The taperangle θ₁ may be different from the taper angle θ₃. That is, aconfiguration of θ₁>θ₃ or η₁ _(l) <θ₃ can be employed. Although FIG. 24exemplified a configuration in which all of the upper surfaces of thesecond conductive layer 120 are covered by the third conductive layer130, it is not limited to this configuration. A part of the uppersurface of the second conductive layer 120 is not covered by the thirdconductive layer 130, and in that area, the upper surface of the secondinsulating layer 120 may be in contact with the insulating layer IL2.

[1-7-8. Modification 8]

As shown in FIG. 25 , although Modification 8 is similar to thestructure of Modification 6(FIG. 23 ), it is different from Modification6 in the structure of the second conductive layer 120 and the thirdconductive layer 130. Specifically, the distance L2 between the outerends of the second conductive layer 120 is smaller than a distance L3between the outer ends of the third conductive layer 130. Consequently,a lower surface 131 is not in contact with the second conductive layer120 in the area of a part of the third conductive layer 130. In FIG. 25, although the configuration in which the lower surface 131 is incontact with the insulating layer IL2 is exemplified, it is not limitedto this configuration. For example, the lower surface 131 may not be incontact with the insulating layer IL2. That is, the insulating layer IL2may not be formed in the vicinity of the lower surface 131, and a cavitymay be formed.

FIG. 26 is a cross-sectional photograph of a transistor according to anembodiment of the present invention (cross-sectional TEM image). In FIG.26 , the gate insulating layer GI1, the first conductive layer 110, thesecond conductive layer 120, the third conductive layer 130, and theinsulating layer IL2 are enlarged and displayed. In the cross-sectionalphotograph shown in FIG. 26 , shapes of each end of the first conductivelayer 110, the second conductive layer 120, and the third conductivelayer 130 are shown by dotted lines. The structure shown in thecross-sectional photograph of FIG. 26 has the same configuration as thestructure shown in FIG. 25 .

2. Second Embodiment

A configuration of a display device 10A according to an embodiment ofthe present invention will be described with reference to FIG. 14 . FIG.14 is a cross-sectional view showing an outline of a display deviceaccording to an embodiment of the present invention. Although thedisplay device 10A shown in FIG. 14 is similar to the display device 10shown in FIG. 1A, the positional relationship between the pixelelectrode PTCO and the common electrode CTCO is different.

As shown in FIG. 14 , the common auxiliary electrode CMTL and the commonelectrode CTCO are provided above the insulating layer IL4. Theinsulating layer IL5 is provided above the common auxiliary electrodeCMTL and the common electrode CTCO. The pixel electrode PTCO is providedabove the insulating layer IL5. The pixel electrode PTCO is connected tothe connecting electrode ZTCO via the opening PCON provided in theinsulating layers IL4 and IL5. As described above, the pixel electrodePTCO may be provided above the common electrode CTCO.

According to the display device 10A of the present embodiment, the sameeffects as those of the display device 10 of the first embodiment can beobtained.

3. Third Embodiment

An entire configuration of the display device described in the firstembodiment and the second embodiment will be described with reference toFIG. 15 to FIG. 17 .

[3-1. Outline of Display Device 20B]

FIG. 15 is a plan view showing an outline of a display device accordingto an embodiment of the present invention. As shown in FIG. 15 , adisplay device 20B includes an array substrate 300B, a seal part 400B, acounter substrate 500B, a flexible printed circuit board 600B (FPC600B), and an IC chip 700B. The array substrate 300B and the countersubstrate 500B are bonded by the seal part 400B. Multiple pixel circuits310B are arranged in a matrix in a liquid crystal area 22B surrounded bythe seal part 400B. The liquid crystal area 22B is an area overlapping aliquid crystal element 410B described later in a plan view. The liquidcrystal area 22B is an area configured to contribute to a display. Theliquid crystal area 22B may be referred to as a “display area”. Thetransistor Tr1 (first transistor) is provided in the liquid crystal area22B (display area).

A seal area 24B provided with the seal part 400B is an area around theliquid crystal area 22B. The FPC 600B is provided in a terminal area26B. The terminal area 26B is an area where the array substrate 300B isexposed from the counter substrate 500B and provided outside the sealarea 24B. The exterior side of the seal area means outside the areaprovided with the seal part 400B and outside the area surrounded by theseal part 400B. The IC chip 700B is provided on the FPC 600B. The ICchip 700B supplies a signal for driving each pixel circuit 310B. Theseal area 24B or an area combined with the seal area 24B and theterminal area 26B is an area that surrounds the liquid crystal area 22B(display area). These areas may be referred to as a “frame area”. Thetransistor Tr2 (the second transistor) is provided in the frame area.

[3-2. Circuit Configuration of Display Device 20B]

FIG. 16 is a block diagram showing a circuit configuration of a displaydevice according to an embodiment of the present invention. As shown inFIG. 16, a source driver circuit 320B and the liquid crystal area 22Bwhere the pixel circuit 310B is arranged are adjacent in the directionD1 (column direction), and the gate driver circuit 330B and the liquidcrystal area 22B are adjacent in the direction D2 (row direction). Thesource driver circuit 320B and the gate driver circuit 330B are providedin the seal area 24B described above. However, the area where the sourcedriver circuit 320B and the gate driver circuit 330B are provided is notlimited to the seal area 24B, and it may be any area as long as it isoutside the area provided with the pixel circuit 310B.

A source wiring 321B extends in the direction D1 from the source drivercircuit 320B and is connected to the multiple pixel circuits 310Barranged in the direction D1. A gate wiring 331B extends in thedirection D2 from the gate driver circuit 330B and is connected to themultiple pixel circuits 310B arranged in the direction D2.

The terminal area 26B is provided with a terminal part 333B. Theterminal part 333B and the source driver circuit 320B are connected by aconnecting wiring 341B. Similarly, the terminal part 333B and the gatedriver circuit 330B are connected by the connecting wiring 341B. Whenthe FPC 600B is connected to the terminal part 333B, an external deviceto which the FPC 600B is connected and the display device 20B areconnected, and each pixel circuit 310B provided in the display device20B is driven by a signal from the external device.

The transistor Tr1 shown in the first embodiment and the secondembodiment is used for the pixel circuit 310B. The transistor Tr2 shownin the first embodiment and the second embodiment is applied to thetransistor included in the source driver circuit 320B and the gatedriver circuit 330B.

[3-3. Pixel Circuit 310B of Display Device 20B]

FIG. 17 is a circuit diagram showing a pixel circuit of a display deviceaccording to an embodiment of the present invention. As shown in FIG. 17, the pixel circuit 310B includes elements such as a transistor 800B, astorage capacitor 890B, and the liquid crystal element 410B. Oneelectrode of the storage capacitor 890B is the pixel electrode PTCO andthe other electrode is the common electrode CTCO. Similarly, oneelectrode of the liquid crystal element 410B is the pixel electrode PTCOand the other electrode is the common electrode CTCO. The transistor800B includes a first gate electrode 810B, a first source electrode830B, and a first drain electrode 840B. The first gate electrode 810B isconnected to the gate wiring 331B. The first source electrode 830B isconnected to the source wiring 321B. The first drain electrode 840B isconnected to the storage capacitor 890B and the liquid crystal element410B. The transistor Tr1 shown in the first embodiment and the secondembodiment is applied to the transistor 800B shown in FIG. 17 . In thepresent embodiment, for convenience of explanation, although 830B isreferred to as a source electrode and 840B is referred to as a drainelectrode, the function of each electrode as a source and a drain may bereplaced.

Each of the embodiments described above as an embodiment of the presentinvention can be appropriately combined and implemented as long as theydo not contradict each other. Further, the addition, deletion, or designchange of components as appropriate by those skilled in the art based oneach embodiment are also included in the scope of the present inventionas long as they are provided with the gist of the present invention.

It is understood that, even if the effect is different from thoseprovided by each of the above-described embodiments, the effect obviousfrom the description in the specification or easily predicted by personsoridnarily skilled in the art is apparently derived from the presentinvention.

What is claimed is:
 1. A display device comprising: a first transistor,the first transistor including: an oxide semiconductor layer; a firstgate electrode facing the oxide semiconductor layer; and a gateinsulating layer between the oxide semiconductor layer and the firstgate electrode, wherein the first gate electrode includes a firstconductive layer formed on the gate insulating layer and having hydrogenstorage properties, a second conductive layer formed on the firstconductive layer and having a lower resistance than the first conductivelayer, and a third conductive layer formed on the second conductivelayer and having hydrogen storage properties, and the first conductivelayer, the second conductive layer and the third conductive layer formsan inclined side surface facing upward.
 2. The display device accordingto claim 1, wherein a thickness of the third conductive layer is lessthan a thickness of the first conductive layer.
 3. The display deviceaccording to claim 1, wherein the first gate electrode includes a fourthconductive layer formed on the third conductive layer and havinghydrogen storage properties, and the fourth conductive layer covers anupper surface and a side surface of the third conductive layer and aside surface of the second conductive layer.
 4. The display deviceaccording to claim 3, wherein the fourth conductive layer covers anupper surface and a side surface of the first conductive layer, and isin contact with the first gate insulating layer.
 5. The display deviceaccording to claim 1, further comprising: a second transistor, thesecond transistor including: a semiconductor layer; a second gateelectrode facing the semiconductor layer; and a second gate insulatinglayer between the semiconductor layer and the second gate electrode; anda first insulating layer covering the semiconductor layer, wherein thefirst insulating layer is arranged in the same layer of the first gateinsulating layer.
 6. The display device according to claim 5, furthercomprising: a display region displaying an image; and a peripheralregion surrounding the display region, wherein a plurality of pixelcircuits are provided in the display region, a driver circuit configuredto drive the plurality of pixel circuits is provided in the peripheralregion, the first transistor is included in one of the pixel circuits inthe display region, and the second transistor is included in the drivercircuit in the peripheral region.
 7. The display device according toclaim 6, further comprising: a first wiring arranged in the same layeras the first gate electrode provided in the peripheral region; and asecond wiring arranged in the same layer as the second gate electrode,wherein the first wiring is connected to the second wiring via a contacthole penetrating the first gate insulating layer and the second gateinsulating layer.
 8. A display device comprising: a first transistor,the first transistor including: an oxide semiconductor layer; a firstgate electrode facing the oxide semiconductor layer; and a gateinsulating layer between the oxide semiconductor layer and the firstgate electrode, wherein the first gate electrode includes a firstconductive layer formed on the gate insulating layer and having hydrogenstorage properties, a second conductive layer formed on the firstconductive layer and having a lower resistance than the first conductivelayer, a third conductive layer formed on the second conductive layerand having hydrogen storage properties, and the third conductive layercovers at least an upper surface and a side surface of the secondconductive layer.
 9. The display device according to claim 8, whereinthe third conductive layer covers an upper surface and a side surface ofthe first conductive layer, and is in contact with the first gateinsulating layer.
 10. The display device according to claim 8, furthercomprising: a second transistor, the second transistor including: asemiconductor layer; a second gate electrode facing the semiconductorlayer; and a second gate insulating layer between the semiconductorlayer and the second gate electrode; and a first insulating layercovering the semiconductor layer, wherein the first insulating layer isarranged in the same layer of the first gate insulating layer.
 11. Thedisplay device according to claim 10, further comprising: a displayregion displaying an image; and a peripheral region surrounding thedisplay region, wherein a plurality of pixel circuits are provided inthe display region, a driver circuit configured to drive the pluralityof pixel circuits is provided in the peripheral region, the firsttransistor is included in one of the pixel circuits in the displayregion, and the second transistor is included in the driver circuit inthe peripheral region.
 12. The display device according to claim 11,further comprising: a first wiring arranged in the same layer as thefirst gate electrode provided in the peripheral region; and a secondwiring arranged in the same layer as the second gate electrode, whereinthe first wiring is connected to the second wiring via a contact holepenetrating the first gate insulating layer and the second gateinsulating layer.